Traditionally a uniprocessor comprises a plurality of hardware elements individually controlled by signals generated by a control unit by decoding instructions under clock timing control. As more and more hardware elements can be accommodated on a chip or module, the availability of signal paths between chips or modules to accommodate control signals becomes critical, assuming plural chips or modules are required to provide the aggregate of functions desired. Obviously, the path problem disappears when all the function is accommodated in a single chip or module.
An approach to overcoming the control signal path problem is set forth in United Kingdom Patent Specification No. 1225253 which discloses a multi-module system which partly decodes an instruction in a common controller and completes the decoding independently in each module. Synchronization is obtained by feedback signals from the modules to the common controller which is counter driven, a full set of completion signals being required for the counter of the common controller to be advanced, many advances equaling one instruction. Each module has its own driving counter, selectively advanced by attainment of a particular count by the common controller counter.
Partly decoded control signals are smaller in number than fully decoded control signals but the signals, together comprising the instructions, per se, comprise the minimum control signal set and can be used, provided that full decoding is provided on each module rather than the partial decoding of the aforesaid specification. However, this introduces its own set of problems since the synchronizing control provided by a common controller with feedback, automatically disappears. To merely provide common clock timing is not sufficient since any error, looping or blockage in a module is not susceptible to correction by the action of clock timing alone. To decrease the transmitted control signal set and increase the intermodule feedback signals correspondingly is of no great advantage. Further, since a failed module is still, as far as it is concerned, satisfactorily digesting an instruction, externally applied instruction driven diagnostic tools will be effective only on good modules. What is required is a mechanism that will restore synchronism and/or external availability and which is inexpensive in required intermodule signal paths.